1. Field of the Invention
The present invention pertains to voltage controlled oscillators and more particularly to voltage controlled ring oscillators that are commonly utilized in phase locked loop control systems.
2. Related Prior Art
Oscillators may occur in many forms. The simplest form of an oscillator is an amplifier with positive feedback. This oscillator is one which generates a signal where the output voltage oscillates, meaning that it swings up and down in a regular pattern. This signal may be a simple wave, such as a sine wave, square wave, sawtooth wave, etc. or a more complicated waveform.
Prior art in use for voltage controlled oscillators consists of two basic types of circuits, bi-stable multi-vibrators and ring oscillators. Ring oscillators are of importance as relating to the present invention. There are several circuit design techniques for implementing current or voltage controlled ring oscillator designs. A ring oscillator consists of a multiplicity of stages connected in such a manner as to provide an effective phase inversion allowing oscillation. Typically, three stages are used to provide the instability and the positive feedback necessary for oscillation. Less than three stages tend to be stable and do not oscillate freely.
Ring type oscillators may be grouped essentially into two categories based upon the design of individual stages used in the ring. These two categories are conventional CMOS current starved inverters and differential current switch amplifiers. These are the most common types of CMOS ring oscillators.
FIG. 1 is a circuit diagram for a single stage of a differential current switch ring type oscillator. Parallel CMOS circuits 12 and 14 are connected to voltage source 16, V.sub.DD, through a P channel FET 18. Gate 19 of FET 18 is connected to P.sub.BIAS, with its source 20 connected to V.sub.DD and its drain 22 connected to the sources 24 and 26 of P-type FETs 28 and 30, respectively, of CMOS circuits 12 and 14. P.sub.BIAS connects to gates of additional FET's, within other stages of the ring oscillator.
FET 28 has its gate 32 connected to input IN while FET 30 has its gate 34 connected to IN. Drain 36 of P-type FET 28 is connected to drain 38 of N-type FET 40 of CMOS circuit 12 and drain 42 of P-type FET 30 is connected to drain 44 of N-type FET 46 in CMOS circuit 14. Output OUT is received from the gate 50 and the drain 44 of N-type FET 46. The output OUT is taken from the gate 48 and the drain 38 of the FET 40. Sources 52 and 54 of FETs 40 and 46 are connected to voltage source V.sub.SS.
In operation, the output and inverted output of this first stage is fed as inputs to the next stage. The outputs of this second stage provide the inputs for the next stage etc., until the last stage whose output and inverted output are fed to the input and inverted input of the stage illustrated. This is done in a ring or circular fashion, which gives it its name of a ring type oscillator. A logical inversion must occur within the ring.
It is to be noted that FET's 40 and 46 act as the loads for the differential current switch. While the loads are shown as FET's, any load is sufficient as long as a current and voltage relationship can be established to provide greater than unity gain for the stage.
The differential current switch circuit design type of ring oscillator has the advantage of being relatively both process and power supply voltage insensitive. This circuit, however, provides very small differential output voltages at each stage. Each stage must be buffered with an amplifier arrangement having its own sensitivities, to drive conventional CMOS logic. Simple analysis shows that this circuit may be implemented as either a PMOS or NMOS based switch, each type having its own advantages and disadvantages.
FIG. 2 is a circuit diagram for a single stage of a current starved inverter type ring oscillator. CMOS circuit 52 includes P-type FET 54 and N-type FET 56 connected at the drain 58 of FET 54 and the drain 60 of FET 56. Source 62 of FET 54 is connected to voltage source V.sub.DD 64 through P-type FET 66, having its gate 68 connected to P.sub.BIAS with its drain 70 connected to source 62 and its source 72 connected to V.sub.DD 64. Source 74 of N-type FET 56 is connected to voltage source V.sub.SS 76 through N-type FET 78 having its gate 80 connected to N.sub.BIAS, its drain 82 connected to source 74 and its source 84 connected directly to V.sub.SS 76. Input IN is fed to gates 86 and 88 of P-type FET 54 and N-type FET 56 respectively. Output OUT is taken from the connection of drain 58 of FET 54 and drain 60 of FET 56.
Only a first stage is illustrated, with the additional stages being identical, the combination of which forms a ring which provides the ring oscillator. In the operation of the total ring circuit, the output from this first stage provides the input for the next stage of the ring oscillator. The output of the second stage provides the input for the third stage etc., until the last stage whose output adds to the input of the first stage.
The current starved inverter type ring oscillator provides the advantage of a very straightforward interface with conventional CMOS logic circuits, since its internal voltage swing approximates conventional rail to rail CMOS logic. This circuit design, however, is sensitive to power supply voltage and inverter threshold effects as well as the nonidealities of the MOS devices due to process variance.
Both types of ring oscillators described usually incorporate external CMOS stage buffering for improved drive characteristics and load independence.